One or more aspects of the present invention relate in general to the field of hierarchical cache structures, and in particular to handling hierarchical cache structures.
A cache memory, or cache, is a high speed memory positioned between a processor and main storage, to hold recently accessed main storage data. Whenever data in storage is accessed, it is first determined whether or not the data is in the cache and, if so, it is accessed from the cache. If the data is not in the cache, the data is obtained from the main storage and the data is also stored in the cache, usually replacing other data which had been stored in the cache memory. Usually a cache hierarchy is implemented, where multiple levels of cache exist between the processor and main storage. As one gets farther away from the processor, each cache gets larger, slower and cheaper per byte. The cache closest to the processor is called first level cache, the next-closest cache is called second level cache, and the next-closest cache is called third level cache, and so on.
One processor may have multiple first level caches, such as one first level cache for data and/or operands and one first level cache for instructions. That means that the first level cache is split in a first level data cache and in a first level instruction cache. A unified second level cache may be connected to multiple first level caches where the first level caches are either for the same processor or for multiple processors in a multi-processor system. Additionally the second level cache is the superset of the first level cache, i.e. all cache-line data of the first level cache is also in the second level cache.
Further the second level cache may also be split in a second level data cache and in a second level instruction cache, wherein the first level instruction cache is connected to the second level instruction cache and the first level data cache is connected to the second level data cache. A unified third level cache may be connected to multiple second level caches.
In a virtual memory system, a memory access issued by an instruction is usually a virtual address, or logical address, or effective address known to the associated program. The real address, or absolute address, or physical address in main memory associated with a virtual address can be determined through a translation process. The translation process is a multi-cycle multi-step process that involves table lookups to get the real address. To speed up the translation, a translation lookaside buffer is used. The translation lookaside buffer holds the virtual address and corresponding real address for recent translations. Depending on architectural requirements, the translation lookaside buffer uses more fields than just the virtual address and corresponding real address. The portion of an address that is subject to translation is known as a page. A cache has a directory array which holds the addresses of the data currently in the cache. Each address corresponds to a unit of storage called a cache-line.
In the Patent Application Publication US 2009/0216949 A1, which is hereby incorporated herein by reference in its entirety, a method and system for a multi-level virtual/real cache system with synonym resolution are disclosed. A disclosed embodiment includes a multi-level cache hierarchy, including a set of first level caches associated with one or more processor cores and a set of second level caches, wherein the set of first level caches are a subset of the set of second level caches, wherein the set of first level caches underneath a given second level cache are associated with one or more processor cores.
A virtually indexed first level cache and a real indexed second level cache allow faster access to the first level cache, without waiting for the translation lookaside buffer access. It requires that the second level cache sends the synonym to the first level cache for cross interrogations commands.